Some terms used in semiconductor testing industry will now be illuminated. The definitions are presented informally to aid in the understanding of the reader and therefore should not be considered binding:
An integrated circuit (IC) is a small electronic device made out of a semiconductor material. A wafer is a thin slice of semiconductor material, such as silicon, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation), etching, and deposition of various materials.
A wafer is usually made up of many single units also called dice (one unit=die, two or more units=dice or dies). After the fabrication process is completed, the wafer will be cut during the assembly process and each die may be connected into a package using aluminum (or occasionally gold) wires which are welded to pads, usually found around the edge of the die.
There are various testing stages. For example, sort (also known as wafer probe) is done while the units are still at wafer level. For example, final test is done after the units have been packaged.
A “touchdown” is the term used when the interface unit (for example at Sort—probe-card or for example at Final Test—contactor or load-board) “touches” the unit under test.
Note that the term “device” may have many meanings in semiconductor testing, including integrated circuits, product type, wafer or die and the meaning should be construed based on the context.
The term “lot” may also have more than one meaning in semiconductor testing. Typically although not necessarily in fabrication, E-test (Electrical Test or Parametric Electrical Test), and sort test, a (fabrication) “lot” refers to a plurality of wafers that were manufactured at the same time, whereas in burn in, final test, and system validation, a (n assembly) “lot” typically although not necessarily refers to a plurality of units that were tested in the same batch.
The testing of a group of integrated circuit (IC) devices may be performed by various general methods. At the highest level, these methods may be distinguished by whether they involve testing devices a single one at a time i.e. “sequentially”, or whether testing occurs on several at the same time, i.e. in “parallel”. Complex products such as CPUs are typically tested a single device at a time, while memory devices are most often tested in parallel. The grouping of devices being tested together in a parallel test configuration at the wafer-sort operation is often referred to informally as a “touchdown”.
A manufacturing test flow for a set of IC devices will often be composed of multiple successive test operations, also sometimes referred to as “test socketings” or “test sockets”. Within each test operation, the test program for that particular test operation will typically be executed under control of an automated test equipment (ATE) system, often aided by built-in self-test (BIST) circuits included on-chip. The test program includes at least one test executed in order to determine if the device under test is good or bad. The tests in the test program are typically executed one at a time on a device, but this is not binding. Each test within a test program has a characteristic test time. The sum of the test times for the set of tests within a test program for a given device is the total device test time of that device in that test operation.
The minimum test time required to execute an individual test within a test program on a device will naturally vary somewhat from one device to another. Normally, variation in the minimum test time required to execute any given test is the result of the natural variation in the physical characteristics of IC sub-components, such as transistors, resistors, capacitors, making up the IC circuits. The variation is ultimately the result of less-than-perfect fabrication capabilities, causing structures within the microcircuits such as line-width, film-thickness and the like to vary somewhat within an IC, as well as varying from IC to IC, and from fabrication lot to fabrication lot. Such variation is generally unavoidable in IC fabrication processes, and results in a distribution of electrical performance in a population of finished IC devices that is usually “normal”, i.e. Gaussian, in nature. IC test conditions and test algorithms are sometimes designed to accommodate this normal variation, typically either running tests slowly enough to allow even the slowest performing devices to keep up with the test operations, or employing adaptive test algorithms that adjust the speed of test according to inherent device performance.
As mentioned, the above source of test-time variation is intrinsic to IC fabrication technology. Moreover, the performance of any given device can also be greatly degraded by faulty fabrication processing, potentially creating or depositing discrete defects within the circuits of the device or skewing the dimensions of IC sub-component structures, leading to aberrant circuit behavior. In most cases, such issues will actually cause the finished IC device to be non-functional, resulting in test failure. However, if the issue is relatively minor the device may remain functional, and will simply exhibit highly degraded electrical performance. In this case, such a device may appear as an “outlier” in the overall test-time distribution of the population of IC devices that is otherwise Gaussian, testing much more slowly than the group of normal devices.
There will now be described the commonly used industry practices of sequential and parallel IC testing.
In sequential testing, the total test time for a set of devices is simply the sum of the total test times for the individual devices in the group. This is illustrated in FIG. 1, where the total test time of the twelve tested devices equals 260 seconds (i.e. 20 for device A1+20 for device B1+20 for device C1+20 for device D1+20 for device A2+20 for device B2+20 for device C2+20 for device D2+30 for device A3+20 for device B3+20 for device C3+20 for device D3). Note that since each device is tested independently of the others, individual device test times may be allowed to vary, for example in FIG. 1 device C2 and device A3 each have a test time of 30 seconds compared to test times of 20 seconds each for the other devices. Alternatively, if testing is done in such a way that the tests within the test program are always executed slowly enough to accommodate even the slowest normal devices encountered, test-time will be constant. Either way, the total test-time for a set of devices will simply be the sum of the test-times of the individual devices.
If testing is done on a group of devices in parallel and in a synchronized fashion, all devices within the group will complete testing at the same time. This is because in a synchronous test environment the tester regulates test operations such that each test in the test program occurs simultaneously and synchronously on all devices being tested in parallel. In this case, the tester hardware driving signals are actually shared between all devices tested in parallel. In order to ensure that all normal devices within the group can keep up with the synchronized test execution imposed by the ATE, the rate of testing is selected such that even the slowest normal devices that meet specifications are accommodated. Devices are no longer tested independently; testing instead occurs between devices in lockstep. When the testing of the group of devices within the parallel group is complete, testing will progress to the next parallel group (i.e. to the next group of devices to be tested in parallel).
In such a synchronous parallel test environment, the total test time for a set of devices is the sum of the total test times for the individual parallel groups, with identical test-time for each device and therefore for each parallel group. This is illustrated in FIG. 2 where the same group of 12 devices which were tested sequentially in the example of FIG. 1 is tested instead in the example of FIG. 2 in a synchronous parallel test environment with three parallel groups of four devices each successively tested. The test time for each device (and therefore for each parallel group) is limited by the test time of the slowest device from any of the parallel groups (i.e. from the group of devices being tested), in this example 30 seconds (recall that 30 seconds was the test time of slowest devices C2 or A3—see FIG. 1). Therefore the total test time is 90 seconds (i.e. 30 seconds for each parallel group×3 parallel groups). The benefit of such a parallel test operation over a sequential one is that in approximately the same amount of time required to test one device all the devices in the parallel group can be tested, effectively increasing the testing capacity.
However, if testing of the group of devices within a parallel group is not forced to be synchronous (i.e. is asynchronous), the test time of each independent device within the group may in some cases vary. An example of such an environment would be one involving on-chip Built-In-Self-Test (BIST) methods, allowing independent execution of test algorithms for each device. Because in this case the execution paths of test algorithms may vary between individual devices, variable test execution time between devices is possible.
In such an asynchronous parallel test configuration the test-time for each parallel group is determined by the device in that parallel group with the longest test time (“the weakest link in the chain”). For example, if there are 4 devices being tested in parallel and 3 of them complete testing in less than 20 seconds, while the fourth device requires 30 seconds to complete testing, then the overall test time of the parallel group will be 30 seconds. Only after all 4 devices in the parallel group have completed testing can tester resources be redeployed to the next (untested) group of 4 devices. In this example, although the parallel test arrangement allows the 4 devices to complete testing much more quickly than they would if tested sequentially, the slow fourth device adds an extra 50% to the parallel group test time that would be required if the slow device were eliminated from the group. This is illustrated in FIG. 3, where the same group of devices tested in a sequential or parallel synchronous test environment in the example of FIG. 1 or FIG. 2 respectively are instead tested in an asynchronous parallel testing environment. The first parallel group in FIG. 3 has a 20 second test time for each of the four included devices and therefore the test time of the first group is 20 seconds. The second parallel group in FIG. 3 has a 20 second test time for each of the three included devices and a 30 second test time for the fourth included device (device C2) and therefore the test time of the second group is 30 seconds. Similarly, the third parallel group in FIG. 3 has a 20 second test time for each of three included devices and a 30 second test time for the fourth included device (device A3) and therefore the test time for the third group is 30 seconds. Total test time is therefore 80 seconds (i.e. 20 seconds for the first parallel group+30 seconds for the second parallel group+30 seconds for the third parallel group)
The problem of slow device test time is exacerbated by the trend in IC test technology towards higher levels of test parallelism. As the number of devices included in a parallel group increases, with advancing IC manufacturing and test technology, so does the probability that at least one of those devices will exhibit abnormally slow test-time. This is because even at the low defect density at which random discrete defects occur within modern IC fabrication processes, the probability that at least one IC device within a group of devices to be tested contains a test-time limiting defect is significant, increasing for example exponentially with an increasing number of devices in the parallel group, if Poisson statistics are applicable. For example, if 1% of individual devices contain fabrication defects causing them to be abnormally slow to test, the probability of finding such a device in a parallel test group sized at 16 devices is fairly low, while the probability of finding such a device in a parallel test group sized at 256 devices is highly likely. For the conditions given in this example, assuming binomial statistics, the probability of finding an abnormally slow device in the ×16 grouping is only 15%, while for the ×256 grouping the probability is 92%. For the larger grouping, in fact, the test time of every parallel group is virtually assured to be limited by aberrant devices.
As illustrated above, even when the fraction of abnormally slow-to-test devices is relatively low, the aberrant devices may have a significant impact on the overall test time of the test operation, especially in a highly parallel test environment. Further, those skilled in the art will recognize that there is frequently a correlation between devices with abnormal behavior during test and the likelihood of ultimately either failing test operations or exhibiting reliability or performance problems in end-user product applications. Therefore, test capacity in an IC test operation may be significantly limited by abnormal devices, which may individually have little or no value, or in a worse case may in fact contribute to product line reliability or performance issues.